1. Field of the Invention
The present invention relates generally to semiconductor fabrication systems and, more particularly, to semiconductor wafer fabrication systems including one or more process tools.
2. Description of Related Art
Integrated circuits are typically formed by processing several semiconductor wafers as a group or “lot” through a series of wafer fabrication process tools (hereafter, “process tools”). Each process tool typically performs a single wafer fabrication operation upon the semiconductor wafers. The integrated circuits formed in this manner are substantially identical to one another. Following wafer fabrication, the integrated circuits are typically subjected to functional testing, and then separated to form individual integrated circuits called “chips” or “die.” Fully functional die are typically packaged and sold as individual units.
During operation of a process tool, one or more operating conditions are established within the process tool, typically dependent upon input (e.g., control signals) from a centralized manufacturing execution system (MES), or from a human operator. These operating conditions also typically affect a “throughput” of the process tool, where the throughput of the process tool is the number of semiconductor wafers processed by the process tool per unit of time.
For example, in a furnace process tool, a desired or “target” elevated temperature to be maintained within the furnace during operation is selected. In addition, a rate at which the temperature within the furnace is to rise after wafer loading may be selected, and a rate at which the temperature within the furnace is to decrease prior to wafer unloading may also be selected Input from a MES, or an operator of the furnace, may select the target temperature, the temperature “ramp-up” rate, and/or the temperature “ramp-down” rate.
A control system of the furnace is tasked with increasing the temperature within the furnace at the ramp-up rate and decreasing the temperature within the furnace at the ramp-down rate. The amount of time the one or more semiconductor wafers must remain in the furnace may depend on the ability of the furnace control system to establish the selected ramp-up rate and the ramp-down rate. In this situation, the throughput of the furnace is expectedly dependent upon the ability of the furnace control system to establish the selected ramp-up rate and the ramp-down rate. Delays of an operator will also affect the throughput. Due to fierce competition, semiconductor manufacturers are highly motivated to operate process tools at or near their maximum throughputs. In order to do so, semiconductor manufacturers must determine the relationships between throughputs of process tools, and the operating conditions established within the process tools during operation.
A typical MES is capable of performing many important functions, including work in process (WIP) tracking, resource allocation and status, operations scheduling, quality data collection, and process control. However, the typical MES is not configured to determine for example the throughputs of process tools.
A need thus exists in the prior art for means and methods of determining throughputs of process tools, and relationships between throughputs of process tools and operating conditions established within the process tools during operation.